This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. xc2xa7119 from an application for DEVICE FOR CONVERTING BIT RATE OF SERIAL DATA earlier filed in the Korean Industrial Property Office on the Dec. 29, 1997 and there duly assigned Serial No. 75960/1997.
1. Technical Field
The present invention relates to a method and device for converting a bit rate in a specific system and, in particular, to a method and device for converting a bit rate of serial data.
2. Related Art
In general, when data is transmitted between systems or units in a specific system in an electronic communication system, bit rates in the systems or units may be different from each other. That is, when data is transmitted and received between systems or units of a system which have bit rates different from each other, one side is at a relatively high rate and other side is at a relatively low rate. Accordingly, the relatively low rate unit or system requires a bit rate converter in order to process high rate input data at a low rate. A method for converting the bit rate of data (especially, serial data) employed in current communication systems is explained below. When a low rate unit or system receives high rate serial data, the high rate serial data is converted into parallel data, and this parallel data is latched with a low rate clock having a cycle corresponding to an actual data processing rate and a different phase using a time slot method. The latched data is converted into serial data according to the low rate clock having a cycle corresponding to the actual data processing rate. By doing so, the high rate serial data is converted into low rate serial data. However, when high rate 8-bit serial data is converted into low rate data, there is a time delay corresponding to eight cycles of a processing clock for the high rate data. On the other hand, when low rate 8-bit serial data is converted into high rate serial data via parallel conversion processing, this also produces a time delay corresponding to one cycle of a processing clock for low rate data.
Furthermore, processing of serial data in parallel requires logic for converting serial data into parallel data, logic for converting the parallel data into serial data, and a plurality of flip-flops for latching data when the serial data is converted into parallel data. Specifically, one flip-flop is needed for each bit of data. Accordingly, many components are required to construct the bit rate conversion device. This increases the cost and complicates the logic circuitry.
The following patents are considered to be representative of the prior art, and are burdened by the disadvantages set forth herein: U.S. Pat. No. 4,317,198 to Johnson, entitled Rate converting Bit Stram Demultiplexer And Multiplexer, U.S. Pat. No. 5,247,652 to Uda, entitled parallel To Serial Converter Enabling Operation At A High Bit Rate With Slow Components By Latching Sets Of Pulses Following Sequential Delays Equal To Clock Period, U.S. Pat. No. 5,357,447 to Ichiyoshi, entitled Rate Conversion Apparatus, U.S. Pat. No. 5,359,605 to Urbansky et al., entitled Circuit Arrangement For Adjusting The Bit Rates Of Two Signals, U.S. Pat. No. 5,396,598 to Andersen et al., entitled Event-Driven Signal Processor Interface Having Multiple Paralleled Microprocessor-Controlled Data Processors For Accurately Receiving, Timing And Serially Retransmitting Asynchronous Data With Quickly Variable Data Rates, U.S. Pat. No. 5,706,438 to Choi et al., entitled Data Transmission Device For Transmitting Converted Data At A Controlled Transmission Rate, and U.S. Pat. Re.35,254 to Chaisemartin et al., entitled Conversion Device For Doubling/Dividing The Rate Of A Serial Bit Stream.
It is, therefore, an object of the present invention to provide a method and device for converting the bit rate of serial data using a small number of logic elements and without processing the data in parallel.
To achieve the above objects, there is provided a method and device for converting high rate serial data into low rate serial data. The device of the present invention includes: first and second clock application parts for selectively generating a high rate clock and a low rate clock according to a selection signal; a first bit rate conversion part for receiving and latching the high rate serial data according to the high rate clock from the first clock application part, and for outputting the latched data at a low rate according to the low rate clock; a second bit rate conversion part for receiving and latching the high rate serial data according to the high rate clock from the second clock application part, and for outputting the latched data at a low rate according to the low rate clock; a first selector for receiving the output of the first bit rate conversion part and the high rate serial data, and for selectively outputting them; a second selector for receiving the output of the second bit rate conversion part and the high rate serial data, and for selectively outputting them; a selection part for controlling outputting of the two input signals applied to the first and second selectors; and a third selector for receiving the outputs of the first and second bit rate conversion parts, and for sequentially outputting the high rate serial data at the low rate clock.